{"id":620,"date":"2024-04-05T12:08:22","date_gmt":"2024-04-05T03:08:22","guid":{"rendered":"https:\/\/camris.ist.nagasaki-u.ac.jp\/?p=620"},"modified":"2024-04-19T10:40:48","modified_gmt":"2024-04-19T01:40:48","slug":"%e8%ac%9b%e7%be%a9-%e4%ba%ba%e6%9d%90%e8%82%b2%e6%88%90%ef%bc%9a%e9%95%b7%e5%b4%8e%e5%a4%a7%e5%ad%a6%e5%ad%a6%e7%94%9f%e3%83%bb%e6%95%99%e8%81%b7%e5%93%a1%e5%90%91%e3%81%91-2024%e5%b9%b4%e5%ba%a6tsm","status":"publish","type":"post","link":"https:\/\/camris.ist.nagasaki-u.ac.jp\/?p=620","title":{"rendered":"[\u8b1b\u7fa9] \u4eba\u6750\u80b2\u6210\uff1a\u9577\u5d0e\u5927\u5b66\u5b66\u751f\u30fb\u6559\u8077\u54e1\u5411\u3051 2024\u5e74\u5ea6TSMC\u300cAdvanced CMOS Technology-Device, Process, Design,and Package\u300d\u8b1b\u7fa9\u914d\u4fe1\u3092\u8b1b\u7fa9\u5ba4\u9650\u5b9a\u3067\u53d7\u4fe1\u30fb\u958b\u8b1b"},"content":{"rendered":"\n

CAMRIS\u3067\u306f\uff0c\u9577\u5d0e\u5927\u5b66\u306e\u5b66\u751f\u30fb\u6559\u8077\u54e1\u5411\u3051\u306b\uff0cTSMC\u793e<\/a>\u63d0\u4f9b\u306e\u6700\u5148\u7aef\u534a\u5c0e\u4f53\u88fd\u9020\u8b1b\u7fa9\uff62Advanced CMOS Technology-Device,Process,Design,and Package\uff63\u30aa\u30f3\u30e9\u30a4\u30f3\u914d\u4fe1\u3092\u53d7\u4fe1\u3057\uff0c\u8b1b\u7fa9\u5ba4\u5185\u9650\u5b9a\u3067\u958b\u8b1b\u3057\u307e\u3059\uff08URL\u306e\u914d\u5e03\u3092\u7981\u3058\u3089\u308c\u3066\u3044\u307e\u3059\u3002\uff09\u3002\u53d7\u8b1b\u3092\u5e0c\u671b\u3059\u308b\u65b9\u306f\uff0c\u6bce\u56de\u76f4\u63a5\u8b1b\u7fa9\u5ba4\u306b\u6765\u5ba4\u3057\uff0c\u53d7\u8b1b\u767b\u9332\u30d5\u30a9\u30fc\u30e0\u306b\u8a18\u8f09\u306e\u4e0a\uff0c\u53d7\u8b1b\u3055\u308c\u3066\u304f\u3060\u3055\u3044\u3002\u3000<\/p>\n\n\n\n


\u3000\u53d7\u8b1b\u767b\u9332\u30d5\u30a9\u30fc\u30e0<\/strong><\/a>
\u3000\u3000\u3000\u3000\u3000\u3000\u3000
\u8a18<\/p>\n\n\n\n

\u3007\u79d1\u76ee\u540d\u3000\u3000\u3000\u300cAdvanced CMOS Technology-Device, Process, Design, and Package\u300d<\/p>\n\n\n\n

\u3007\u8b1b\u5e2b\u3000\u3000\u3000\u3000\u3000TSMC\u793e<\/a><\/p>\n\n\n\n

\u3007\u958b\u8b1b\u65e5\u6642\u3000\u3000\u30004\u670812\u65e5\uff08\u91d1\uff09\u30fb19\u65e5\uff08\u91d1\uff09\u30fb26\u65e5\uff08\u91d1\uff09
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\u3000\u3000\u3000\u3000\u3000\u3000\u3000\u30006\u67087\u65e5\uff08\u91d1\uff09
\u3000\u3000\u3000\u3000\u3000\u3000\u3000\u3000\u5168\uff18\u56de\u300016\uff1a40\uff5e18\uff1a10
\u3000\u3000\u3000\u3000\u3000\u3000\u3000\u3000\u203b\u8b1b\u7fa9\u5ba4\u306b\u3066\u4e5d\u5927\u3067\u306e\u8b1b\u7fa9\u3092\u30e9\u30a4\u30d6\u53d7\u4fe1\u3057\uff0c\u30d7\u30ed\u30b8\u30a7\u30af\u30bf\uff08\u307e\u305f\u306f\u30e2\u30cb\u30bf\uff09\u3067\u8868\u793a<\/p>\n\n\n\n

\u3007\u8b1b\u7fa9\u5ba4\u3000\u3000\u3000\u3000\u5de5\u5b66\u90e82\u53f7\u9928 23\u756a\u8b1b\u7fa9\u5ba4<\/p>\n\n\n\n

\u3007\u8b1b\u7fa9\u6982\u8981
The series of lectures is to provide an overview of semiconductor industrial practices, covering semiconductor devices, process flow with modules, design & technology co-optimization on FinFET technology, and 3D packaging. It would reveal where advanced CMOS technology is from and heading on, challenges encountered, and resolutions.
\u672c\u8b1b\u7fa9\u3067\u306f\u3001\u534a\u5c0e\u4f53\u30c7\u30d0\u30a4\u30b9\u3001\u30e2\u30b8\u30e5\u30fc\u30eb\u306b\u3088\u308b\u30d7\u30ed\u30bb\u30b9\u30d5\u30ed\u30fc\u3001FinFET\u6280\u8853\u306b\u304a\u3051\u308b\u8a2d\u8a08\u3068\u6280\u8853\u306e\u5354\u8abf\u6700\u9069\u5316\u30013D\u30d1\u30c3\u30b1\u30fc\u30b8\u30f3\u30b0\u306a\u3069\u3001\u534a\u5c0e\u4f53\u7523\u696d\u306b\u304a\u3051\u308b\u5b9f\u8df5\u306e\u6982\u8981\u3092\u8aac\u660e\u3059\u308b\u3002\u5148\u9032\u7684\u306aCMOS\u6280\u8853\u304c\u3069\u3053\u304b\u3089\u6765\u3066\u3001\u3069\u3053\u3078\u5411\u304b\u3063\u3066\u3044\u308b\u306e\u304b\u3001\u76f4\u9762\u3059\u308b\u8ab2\u984c\u3068\u89e3\u6c7a\u7b56\u3092\u660e\u3089\u304b\u306b\u3059\u308b\u3002<\/p>\n\n\n\n

1 Semiconductor introduction(30mins), Device physics(60mins) \/ \u534a\u5c0e\u4f53\u6982\u8ad6(30\u5206)\u3001\u30c7\u30d0\u30a4\u30b9\u7269\u7406(60\u5206)
\u3000\u3000(1)Semiconductor industry, Foundry business, TSMC and JASM overview.
\u3000\u3000(2) Device physics: PN junction, MOS characteristics
\u3000\u3000(1)\u534a\u5c0e\u4f53\u7523\u696d\u3001\u30d5\u30a1\u30a6\u30f3\u30c9\u30ea\u30d3\u30b8\u30cd\u30b9\u3001TSMC\u3068JASM\u306e\u6982\u8981
\u3000\u3000(2)\u30c7\u30d0\u30a4\u30b9\u7269\u7406\uff1aPN\u63a5\u5408\u3001MOS\u7279\u6027
2 Basic process flow introduction \/ \u57fa\u672c\u30d7\u30ed\u30bb\u30b9\u30d5\u30ed\u30fc\u7d39\u4ecb
\u3000\u3000Basic process flow introduction
\u3000\u3000\u57fa\u672c\u30d7\u30ed\u30bb\u30b9\u30d5\u30ed\u30fc\u7d39\u4ecb
3 Process module: Lithography, ETCH \/ \u30d7\u30ed\u30bb\u30b9\u30e2\u30b8\u30e5\u30fc\u30eb\uff1a\u30ea\u30bd\u30b0\u30e9\u30d5\u30a3\u3001ETCH
\u3000\u3000Process module LIT\/ETCHintroduction
\u3000\u3000\u30d7\u30ed\u30bb\u30b9\u30e2\u30b8\u30e5\u30fc\u30ebLIT\/ETCH\u7d39\u4ecb
4 Process module: PVD, CVD, CMP \/ \u30d7\u30ed\u30bb\u30b9\u30e2\u30b8\u30e5\u30fc\u30eb\uff1aPVD\u3001CVD\u3001CMP
\u3000\u3000Process module PVD\/CVD\/CMP introduction
\u3000\u3000\u30d7\u30ed\u30bb\u30b9\u30e2\u30b8\u30e5\u30fc\u30eb PVD\/CVD\/CMP \u7d39\u4ecb
5 (1)Process module: DIF, (2)Manufacturing AMHS \/ (1)\u30d7\u30ed\u30bb\u30b9\u30e2\u30b8\u30e5\u30fc\u30eb\uff1aDIF\u3001(2)\u88fd\u9020AMHS
\u3000\u3000Process module DIF introduction, Manufacturing AMHS introduction
\u3000\u3000\u30d7\u30ed\u30bb\u30b9\u30e2\u30b8\u30e5\u30fc\u30ebDIF\u7d39\u4ecb\u3001\u88fd\u9020AMHS\u7d39\u4ecb
6 Design and Technology Co-Optimization on FinFET technology 1 \/ FinFET\u6280\u8853\u306e\u8a2d\u8a08\u3068\u6280\u8853\u6700\u9069\u5316 1
\u3000\u3000Introduce design differences between FinFET and Planar technology
\u3000\u3000FinFET\u6280\u8853\u3068Planar\u6280\u8853\u306e\u8a2d\u8a08\u4e0a\u306e\u9055\u3044\u3092\u7d39\u4ecb
7 Design and Technology Co-Optimization on FinFET technology 2 \/ FinFET\u6280\u8853\u306b\u304a\u3051\u308b\u8a2d\u8a08\u3068\u6280\u8853\u306e\u6700\u9069\u5316 2
\u3000\u3000Advanced design mythology to optimize PPA (Performance, Power
\u3000\u3000Area) on standard cell, analog, and 3DIC designs
\u3000\u3000Explain the difference between FinFET and Planar using those three examples
\u3000\u3000PPA\uff08\u6027\u80fd\u3001\u6d88\u8cbb\u96fb\u529b\u3001\u9762\u7a4d\uff09\u3092\u6700\u9069\u5316\u3059\u308b\u305f\u3081\u306e\u9ad8\u5ea6\u306a\u8a2d\u8a08\u795e\u8a71\u3002
\u3000\u3000\u9762\u7a4d\uff09\u3092\u6700\u9069\u5316\u3059\u308b\u305f\u3081\u306e\u9ad8\u5ea6\u306a\u8a2d\u8a08\u795e\u8a71
\u3000\u3000FinFET\u3068Planar\u306e\u9055\u3044\u30923\u3064\u306e\u4f8b\u3067\u8aac\u660e\u3059\u308b
8 3D package \/ 3D\u30d1\u30c3\u30b1\u30fc\u30b8
\u3000\u3000Advanced packaging technology of semiconductor devices
\u3000\u3000\u534a\u5c0e\u4f53\u30c7\u30d0\u30a4\u30b9\u306e\u5148\u7aef\u30d1\u30c3\u30b1\u30fc\u30b8\u30f3\u30b0\u6280\u8853<\/p>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

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